The present invention relates to a clock delay adjustment circuit for a semiconductor IC as well as to the control method of the same.
In recent years, there is increased needs for the manufacturing process of the semiconductor IC to be as finer as possible and thus for the IC to be as faster as possible. Along with this, the increase of the device performance is going not to compensate for the manufacturing yields. The design also is being moved toward a way with the least timing margin as possible, such as the statistical STA method. Because of this there is concern about the decreased yields resulting from the incidents of delay faults, in every part in a chip. Not only a few of specific macros included in a semiconductor IC but also the delay fault recovery of many macros randomly dispersed are being required to be recovered. In the following description, a term “macro” means a functional block which constitutes a part of a semiconductor IC circuit.
An exemplary known related art technology which allows the delay fault recovery is a system LSI 1 that is disclosed in Japanese Patent Application Publication No. Hei18(2006)-12046. FIG. 10 shows a configuration of a system LSI 1. The system LSI 1 includes a logic circuit 10, a ROM 20, a clock delay circuit 30, a delay setting circuit 40, delay adjustment nodes 51 and 52, selectors 43 and 61, a checksum computing circuit 60, and a checksum output node 62.
The logic circuit 10 includes multiple circuit blocks 11 such as a CPU, RAM (not shown in the figure), and an I/O circuit, as well as a clock tree buffer 12.
It should be noted here that the circuit block means a logic circuit component which has its function and circuit pattern predetermined, also referred to as a hard macro. The circuit block may be achieved by appropriately laying out some desired circuit pattern on a semiconductor substrate in accordance with the desired system LSI functionality to be achieved. In addition, trace patterns for signals and power supply to the circuit block is coupled thereto along with providing a clock supply path to each circuit block. By doing this a system LSI having some desired functionalities may be configured.
The logic circuit 10 has a clock signal CK0 fed, which is the base of the operation, and the phase of the clock signal CK0 is adjusted in the clock tree buffer 12 then to feed to each circuit block 11 such as CPU.
For instance, assuming that a circuit block 11 is the CPU (referred to as CPU 11 hereinafter), the clock node C of the CPU 11 will receive a clock signal CK2 from the last output of the clock tree buffer 12.
From the intermediate node of the clock tree buffer 12, the clock signal CK1 is provided for feeding to a specific circuit block 20 such as ROM (referred to as ROM 20 hereinafter) under the test in this system LSI. It should be noted that the clock signal CK1 is provided through the clock delay circuit 30.
The clock delay circuit 30 includes multiple delay elements (DL) 31a to 31c connected in series, and a selector 32. The clock delay circuit 30 will output as delayed clock signal DCK the clock signal delayed in these delay elements 31a to 31c in accordance with the designation by the delay adjustment signal DCN.
The delayed clock signal DCK is provided to the clock node C of the ROM 20. The ROM 20 stores any programs to be executed by the CPU 11 or the static data, and reads out the storage contents of the region specified by the addressing signal AD to be outputted as the data RD.
The delay setting circuit 40 stores any appropriate amount of delay adjustment for the clock delay circuit 30, obtained in the test after manufacturing process. For example, multiple series circuits each made of a fuse 41 and a resistance 42 are coupled in parallel between the power supply potential VDD and the ground potential GND, and whether the fuse 41 is connected or disconnected is provided as the delay setting signal DST from the intersection of the fuse 41 and the resistor 42.
The delay setting signal DST is fed to the input terminal A of the selector 43. In addition, the delay adjustment signal DAD from the delay adjustment node 51 is fed to the input terminal B of the selector 43. The selector 43 selects the input terminal A when the normal operation mode is specified by the mode signal MOD provided from the mode designation node 52, while it selects the input terminal B when the test operation mode is specified. Thus selected signal is outputted to the clock delay circuit 30 from the output terminal Q as the delay adjustment signal DCN.
The checksum computing circuit 60 and the selector 61 perform the test after manufacturing process of the system LSI 1. The checksum computing circuit 60 outputs, in response to the clock signal CK2 provided to the clock node C, the address signal ADT sequentially increasing from 0. In addition, along therewith, the read data RD read from each address of the ROM 20 is cumulatively added (with any carry of digit being neglected), and then the result is outputted to the checksum output terminal 62 as the checksum SUM.
Address signal ADT of the checksum computing circuit 60 is fed to the input terminal B of the selector 61. The input terminal A of the selector 61 is provided with the address signal ADR from the CPU 11, then the address signal AD from the output terminal Q of the selector 61 is in turn fed to the ROM 20. The read data RD output from the ROM 20 is provided to both the CPU 11 and the checksum computing circuit 60.
Hereinafter the test adjustment process just after the manufacturing of the system LSI 1 will be described. At first, a test jig such as an LSI tester is coupled to the delay adjustment node 51, the mode designation node 52 and the checksum output node 62, then the mode signal MOD is set to the test operation mode (for example, level “H”). By doing this the input terminal B is selected in the selectors 43 and 61, the delay adjustment signal DAD which is provided from the delay adjustment node 51 will be outputted to the clock delay circuit 30 as the delay adjustment signal DCN. The address signal ADT which is outputted from the checksum computing circuit 60 will be fed to the ROM 20 as the address signal AD.
Next, by setting the delay adjustment signal DAD to 0, a predetermined clock signal CK0 is fed. In correspondence with the address signal ADT sequentially output from the checksum computing circuit 60, the memory contents of the ROM 20 corresponding thereto will be thereby read out and output as the read data RD. In the checksum computing circuit 60 the read data RD sequentially fetched will be cumulatively added so as to output the result as the checksum SUM.
Then, at the point of the time when the checksum SUM for the all storage contents of the ROM 20 is outputted, the value of the checksum SUM will be determined whether to be correct or not in comparison with the value previously calculated based on the storage contents of the ROM 20. Such test using the checksum is performed for one value after another of the adjustable delay adjustment signal DAD. At the time when a correct checksum is obtained, the value of the delay adjustment signal DAD providing the correct value is set to the delay setting circuit 40 as the cut/uncut status of the fuse 41.
As can be appreciated from the foregoing description, a system LSI having passed the test adjustment after the manufacturing process will be used in a device. At this time, the mode designation node 52 will be fixedly coupled to the state level “L” so as to designate the normal operation mode. Since, in this normal mode, the delay setting signal DST being set in the delay setting circuit 40 is fed to the clock delay circuit 30 as the delay adjustment signal DCN, the clock delay circuit 30 outputs a delayed clock signal DCK having some appropriate delay time to feed to the ROM 20. The address signal ADR output from the CPU 11 will be provided as the address signal AD to the ROM 20.
As described above, the system LSI 1 in accordance with the first embodiment has the clock delay circuit 30 and the checksum computing circuit 60 for adjusting, after manufacturing process, the delay time of the clock signal for the ROM 20, as well as the delay setting circuit 40 for storing the adjusted value. In such configuration, even if the clock signal timing is skewed from the designate value due to the dispersion in the manufacturing process, the product after the manufacturing process can be compensated for the clock signal timing accordingly; therefore, such malfunction as the incorrect operation due to the operation noises or the error operation due to the discrepancy of the clock timings may be suppressed, in order to have an advantage for avoiding the incidental occurrence of defective products.
In addition, there is another technology in accordance with Japanese Patent Application Publication No. Hei16(2004)-228504 in which, by measuring the amount of clock delay of any clocks to the internal blocks by using the delay measurement circuit, then adjusting the amount of clock delay of any clocks by using the delay adjustment circuit (corresponding to the clock delay circuit) based on the measurement results, and storing the adjusted value in a nonvolatile memory, unexpected clock delay caused by the product dispersion in the manufacturing process can be compensated for.